1. Field of the Invention
This invention is related to the field of memory controllers and, more particularly, to loopback test functionality for memory controllers and integrated circuits including such memory controllers.
2. Description of the Related Art
As integrated circuits increase in complexity and in the number of transistors included on a given instance of the circuit, the testing capabilities of the circuit increase in importance. The ability to test the circuit with a high level of test coverage (to ensure that the circuit is not defective) and inexpensively is an important component of producing a high quality, affordable, and profitable integrated circuit product.
One mechanism that can be useful for testing on a symmetrical interface is loopback. A symmetrical interface is an interface that has the same protocol and physical attributes in both the transmit and receive directions. For example, the Peripheral Component Interconnect (PCI) Express (PCIe) interface is symmetrical. One or more lanes are configured into a link, and each lane comprises a transmit serial communication and a receive serial communication. Thus, a communication transmitted on the transmit link can fairly easily be returned (or “looped back”) on the receive link. Other interfaces that use loopback testing include Ethernet, for example. Loopback testing allows at-speed, functional test of the interface hardware, all the way to the integrated circuit pins and back. Accordingly, both the functional circuitry and the entire transmission path within the integrated circuit can be tested using loopback. Additionally, the test can be performed inexpensively by coupling the output to the input (possibly with delay for timing purposes and/or minor processing to meet protocol requirements) or coupling a component to the interface, rather than using an expensive at-speed tester.
A memory interface, from a memory controller to one or more memory modules such as Dual-Inline Memory Modules (DIMMs), is not symmetrical. Typically, a unidirectional address/command and address control (row address strobe (RAS), column address strobe (CAS), etc.) interface is provided from the memory controller to the memory modules. A bidirectional data bus and data control (e.g. DQ signals) interface is provided, which flows from the memory controller to the memory modules for a write operation and from the memory modules to the memory controller for a read operation. Accordingly, there is not a natural way to perform loopback testing on the memory interface, to test the memory controller hardware. Typically, expensive tester equipment is used to test the memory controller, increasing the cost of the product.